We publish an extension of openQCD-1.6 with AVX-512 vector instructions using Intel intrinsics.
Recent Intel processors support extended instruction sets with operations on 512-bit wide vectors, increasing both the capacity for floating point operations and register memory.
Optimal use of the new capabilities requires reorganising data and floating point operations into these wider vector units.
We report on the implementation and performance of the AVX-512 OpenQCD extension on clusters using Intel Knights Landing and Xeon Scalable (Skylake) CPUs. In complete HMC trajectories with physically relevant parameters we observe a performance increase of 5% to 10%.
Volume 334 -
The 36th Annual International Symposium on Lattice Field Theory (LATTICE2018) -
Algorithms and Machines
AVX-512 extension to OpenQCD 1.6
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Published on:
May 29, 2019
Abstract
DOI: https://doi.org/10.22323/1.334.0039
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Copyright owned by the author(s) under the term of the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
Copyright owned by the author(s) under the term of the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.