PoS - Proceedings of Science
Volume 287 - The 25th International workshop on vertex detectors (Vertex 2016) - Session: Poster
Readout architecture for the Pixel-Strip module of the CMS Outer Tracker Phase-2 upgrade
D. Ceresa,* A. Caratelli, J. Kaplon, K. Kloukinas, S. Scarfi on behalf of the CMS collaboration
*corresponding author
Full text: pdf
Pre-published on: March 22, 2017
Published on: August 03, 2017
Abstract
The Outer Tracker upgrade of the Compact Muon Solenoid (CMS) experiment at CERN introduces new challenges for the front-end readout electronics. In particular, the capability of identifying particles with high transverse momentum using modules with double sensor layers requires high speed real time interconnects between readout ASICs. The Pixel-Strip module combines a pixelated silicon layer with a silicon-strip layer. Consequently, it needs two different readout ASICs, namely the Short Strip ASIC (SSA) for the strip sensor and the Macro Pixel ASIC (MPA) for the pixelated sensor.

The architecture proposed in this paper allows for a total data flow between readout ASICs of $\sim$100\,Gbps and reduces the output data flow from 1.3\,Tbps to 30\,Gbps per module while limiting the total power density to below 100\,mW/cm$^2$. In addition a system-level simulation framework of all the front-end readout ASICs is developed in order to verify the data processing algorithm and the hardware implementation allowing multichip verification with performance evaluation. Finally, power consumption and efficiency performance are estimated and reported for the described readout architecture.
DOI: https://doi.org/10.22323/1.287.0066
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