Main Image
Volume 299 - The 7th International Conference on Computer Engineering and Networks (CENet2017) - Session III -Information Theory
FPGA Implementation of AES Algorithm Resistant Power Analysis attacks
L. Li,* Y. Zou, G. Jiao
*corresponding author
Full text: pdf
Pre-published on: 2017 July 17
Published on: 2017 September 06
Abstract
In order to be more effectively resist differential power analysis attacks, the improved fixed value masking algorithm is proposed for resource-constrained smart card based on fixed value masking and random masking. Firstly, a number of random numbers are selected and prestored in on-chip ROM for generating the corresponding byte-substitution table. It does not increase much power and hardware resources because the byte-substitution table is pregenerated. Finally, experiments in terms of the second-order differential power
analysis attacks have been carried out on the improved fixed masking. The experimental results show that the proposed AES
algorithm can be effectively resistant to the side-channel attacks with lower computing expenses and higher security.
DOI: https://doi.org/10.22323/1.299.0046
Open Access
Creative Commons LicenseCopyright owned by the author(s) under the term of the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.