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Volume 299 - The 7th International Conference on Computer Engineering and Networks (CENet2017) - Session V - Date Analysis
Designing A Unified Architecture Graphics Processing Unit
L. Wu,* L. Huang, T. Xiong
*corresponding author
Full text: pdf
Pre-published on: 2017 July 17
Published on: 2017 September 06
Graphics Processing Unit (GPU) performs graphics computing and its architecture has developed from the fixed function pipeline to the programmable unified pipeline. Unified architecture promises dynamic load balancing and guarantees the high parallel computing of GPU. This paper presents the design and implementation of a unified architecture GPU. The unified shader is based on the SIMD and SIMT architecture. On the thread level, SIMT guarantees the full-load capability of unified shader by thread managing and scheduling. On the instruction level, SIMD controls the execution of the unified shader hardware unit. We finish the algorithm, architecture design and Verilog RTL implementation. The verification results on FPGA show that the proposed GPU works correctly and its vertex and fragment processing speed reaches one unit per clock cycle.
Open Access
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