PoS - Proceedings of Science
Volume 309 - The 26th International Workshop on Vertex Detectors (Vertex 2017) - Detectors in design and Construction
The LHCb Vertex Locator Upgrade
E. Lemos Cid*, P. Vázquez Regueiro  on behalf of the LHCb collaboration
Full text: pdf
Pre-published on: November 03, 2018
Published on: December 05, 2018
The Vertex Locator (VELO) surrounding the interaction region is used to reconstruct the collision points (primary vertices) and decay vertices of long-lived particles (secondary vertices) of the LHCb experiment. The VELO detector will be changed for the upgrade of the LHCb experiment to be able to run at 5 times higher instantaneous luminosity. The modules will be equipped with 4 silicon hybrid pixel tiles, each read out by 3 VeloPix ASICs. The highest occupancy ASICs will sustain rates of 900 Mhit/s and produce an output data rate of over 15 Gbit/s, with a total rate of 2.9 Tbit/s anticipated for the whole detector. The VELO modules are located in vacuum, separated from the beam vacuum by a thin custom made foil. The foil will be manufactured through a novel milling process and possibly thinned further by chemical etching. The front-end hybrid hosts the VeloPix ASICs and a GBTx ASIC for control and communication. The hybrid is linked to the the the Opto-and-Power Board (OPB) by 60 cm electrical data tapes running at 5 Gb/s. The tapes must be vacuum compatible and radiation hard and are required to have enough flexibility to allow the VELO to retract during LHC beam injection. The OPB is placed immediately outside the VELO vacuum tank and performs the opto-electrical conversion of control signals going to the front-end and of serial data going off-detector. The board is designed around the Versatile Link components developed for high-luminosity LHC applications. From the OPB the detector data are sent through 300 m of optical fibre to LHCb's common readout board (PCIe40). The PCIe40 is an Altera Arria10-based PCI-express control and readout card capable of 100 Gb/s data throughput. The PCIe40 firmware is designed as a series of common components with the option for user-specific data processing. The common components deal with accepting the input data from the detector over the GBT protocol, error-checking, dealing with reset signals, and preparing the data for the computing farm. The VELO specific code would, for example, perform clustering of hits and time reordering of the events scrambled during the readout. An additional challenge of the sensor design is the non uniform nature of the radiation damage, which results in requiring a guard ring with excellent high voltage control. The performance of the prototype sensors has been investigated in a test beam, exploring tests of irradiated samples.
DOI: https://doi.org/10.22323/1.309.0002
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