We present two designs of a dual-channel VCSEL driver ASIC, LOCld130 and LOCld65, for detector front-end readout via optical links. Each channel of the driver is designed to operate up to 5.12 Gbps or 14 Gbps respectively. They are implemented in commercial 130-nm and 65-nm CMOS technologies. Techniques that are adopted to extend the bandwidth are multiple stages, shared inductive peaking, active feedback and passive R-C. In the typical case the 5.12-Gbps driver dissipates 56 mW/channel (VCSEL included) and the 14-Gbps 58 mW/channel. LOCld65 will be tested in November 2017 and LOCld130 will be submitted for fabrication in the spring of 2018.