PoS - Proceedings of Science
Volume 313 - Topical Workshop on Electronics for Particle Physics (TWEPP-17) - Programmable Logic Design Tools and Methods
New slow-control FPGA IP for GBT based system and status update of the GBT-FPGA project
J.M. Mendez*, S. Baron, A. Caratelli and P.V. Leitao
Full text: pdf
Pre-published on: March 05, 2018
Published on: March 20, 2018
Abstract
The GBT-FPGA, part of the GBT (GigaBit Transceiver) project framework, is a VHDL-based core designed to offer a back-end counterpart to the GBTx ASIC, a radiation tolerant 4.8 Gb/s optical transceiver. The GBT-SCA (Slow Control Adapter) radiation tolerant ASIC is also part of the GBT chipset and is used for the slow control in the High Energy Physics experiments. In this context, a new VHDL core named GBT-SC has been designed and released to handle the slow control fields hosted in the serial GBT frame for the GBTx and GBT-SCA. This paper presents the architecture and performance of this new GBT-SC module as well as an outline of recent GBTFPGA core releases and future plans.
DOI: https://doi.org/10.22323/1.313.0083
How to cite

Metadata are provided both in "article" format (very similar to INSPIRE) as this helps creating very compact bibliographies which can be beneficial to authors and readers, and in "proceeding" format which is more detailed and complete.

Open Access
Creative Commons LicenseCopyright owned by the author(s) under the term of the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.