The increase of the leakage current of NMOS transistors in detector readout chips in certain 130 nm CMOS technologies during exposure to ionising radiation needs special consideration in the design of detector systems, as this can result in a large increase of the supply current and power dissipation. As part of the R&D program for the upgrade of the ATLAS inner detector tracker for the High Luminosity upgrade of the LHC at CERN, a dedicated set of irradiations have been carried out with the Cobalt-60 gamma-ray source at the Brookhaven National Laboratory. Measurements will be presented that characterise the increase in the digital leakage current in the 130 nm-technology ABC130 readout chips. The variation of the current as a function of time and total ionising dose has been studied under various conditions of dose rate, temperature and power applied to the chip. The range of variation of dose rates and temperatures has been set to be close to those expected at the High Luminosity LHC, i.e. in the range 0.6 krad/h - 2.5 krad/h and between -10°C and $+$10°C. Two of the chips under test were pre-irradiated with high doses of X-rays at Rutherford Appleton Laboratory. The results show the dependence of the leakage current with the parameters under study and provide valuable information for the understanding of the underlying mechanisms responsible for radiation damage in transistors and detector readout chips.