The VMM is a custom Application Specific Integrated Circuit (ASIC). It will be used in the front- end readout electronics of both the Micromegas and sTGC detectors of the New Small Wheel upgrade of the ATLAS experiment at CERN. It is being developed at Brookhaven National Laboratory and fabricated in the 130nm Global Foundries 8RF-DM process (former IBM 8RF- DM). The 64 channels ASIC has highly configurable parameters and is able to handle signals of opposite polarities and a high range of capacitances while being low noise and low on power consumption. The VMM has four independent data output paths. First is the “precision” (10-bit) amplitude and (effective) 20-bit time stamp read out continuously (250 ns dead-time per channel) or at when a trigger occurs. Second, a serial output called Address in Real Time (ART). This is the address of the channel which had a signal above threshold within the bunch crossing clock. Third, the parallel prompt outputs from all 64 channels in a variety of selectable formats (including a 6-bit ADC). Finally a multiplexed analogue amplitude and timing outputs in which the ASIC provides analogue outputs to be digitised externally. The ASIC has undergone 3 versions. Version 3, was submitted in 2016 in a dedicated run and has all the design features including the deep readout buffer logic and SEU mitigation circuitry for the configuration registers, the state machines, and the FIFO pointers. The device is packaged in a Ball Grid Array with outline di- mensions of 21 × 21 mm$^2$ and is being tested for the last years. Since few bugs already found, a version called VMM3a was submitted in October 2017 addressing them. The VMM3 was tested with Micromegas prototype detectors and performance is reported.