We have developed an updated Daughterboard design for control and readout of the upgraded ATLAS Hadronic Tile Calorimeter electronics for HL-LHC. In the new design, four SFP+ modules
handle: four 9.6 Gbps uplinks operated by two Kintex Ultrascale+ FPGAs, and two 4.8 Gbps downlinks operated by two GBTxs. The uplink sends continuous high-speed readout of digitized PMT
samples, while the downlink receives control, configuration and LHC timing. Triple Mode Redundancy (TMR), Forward Error Correction (FEC) and CRC (Cyclic Redundancy Check) strategies, plus a double redundant design with radiation tolerant components, minimize single failure
points and improves resistance to single-event upsets caused by hadronic radiation. Preliminary
TID and NIEL tests were performed following the ATLAS policy on radiation tolerant electronics
and those specified in the European Space Components Coordination specification 22900 (ESCC22900)
ATLAS Tile Calorimeter Link Daughterboard
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Pre-published on:
May 20, 2019
Published on:
July 25, 2019
Abstract
DOI: https://doi.org/10.22323/1.343.0024
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Copyright owned by the author(s) under the term of the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
Copyright owned by the author(s) under the term of the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.