PoS - Proceedings of Science
Volume 343 - Topical Workshop on Electronics for Particle Physics (TWEPP2018) - Posters
ATLAS Tile Calorimeter Link Daughterboard
E. Valdes Santurio*, S. Silverstein and C. Bohm
Full text: pdf
Pre-published on: May 20, 2019
Published on: July 25, 2019
We have developed an updated Daughterboard design for control and readout of the upgraded ATLAS Hadronic Tile Calorimeter electronics for HL-LHC. In the new design, four SFP+ modules
handle: four 9.6 Gbps uplinks operated by two Kintex Ultrascale+ FPGAs, and two 4.8 Gbps downlinks operated by two GBTxs. The uplink sends continuous high-speed readout of digitized PMT
samples, while the downlink receives control, configuration and LHC timing. Triple Mode Redundancy (TMR), Forward Error Correction (FEC) and CRC (Cyclic Redundancy Check) strategies, plus a double redundant design with radiation tolerant components, minimize single failure
points and improves resistance to single-event upsets caused by hadronic radiation. Preliminary
TID and NIEL tests were performed following the ATLAS policy on radiation tolerant electronics
and those specified in the European Space Components Coordination specification 22900 (ESCC22900)
DOI: https://doi.org/10.22323/1.343.0024
How to cite

Metadata are provided both in "article" format (very similar to INSPIRE) as this helps creating very compact bibliographies which can be beneficial to authors and readers, and in "proceeding" format which is more detailed and complete.

Open Access
Creative Commons LicenseCopyright owned by the author(s) under the term of the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.