Main Image
Volume 343 - Topical Workshop on Electronics for Particle Physics (TWEPP2018) - Posters
A Delay Locked Loop for Time-to-Digital Converters with Quick Recovery and Low Hysteresis
B. Van Bockel,* J. Prinzie, Y. Coa, P. Leroux
*corresponding author
Full text: pdf
Pre-published on: 2019 May 20
Published on: 2019 July 25
Abstract
This paper proposes the simulation results of a 1 GHz Delay Locked Loop (DLL) designed in a 65 nm CMOS technology. The circuit was designed for harsh environments, in particular ionizing radiation. A novel phase detector consisting of an improved bang-bang phase detector and a 3-state controller was introduced, leading to a a single event recovery time of less than 1 us. The DLL is used inside a Time to digital converter, and achieves an in lock hysteresis of only 500 fs.
DOI: https://doi.org/10.22323/1.343.0027
Open Access
Creative Commons LicenseCopyright owned by the author(s) under the term of the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.