A Delay Locked Loop for Time-to-Digital Converters with Quick Recovery and Low Hysteresis
B. Van Bockel*, J. Prinzie, Y. Coa and P. Leroux
May 20, 2019
July 25, 2019
This paper proposes the simulation results of a 1 GHz Delay Locked Loop (DLL) designed in a 65 nm CMOS technology. The circuit was designed for harsh environments, in particular ionizing radiation. A novel phase detector consisting of an improved bang-bang phase detector and a 3-state controller was introduced, leading to a a single event recovery time of less than 1 us. The DLL is used inside a Time to digital converter, and achieves an in lock hysteresis of only 500 fs.
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