With future pixel ASICs trending towards mega-frame rate readout, the development of ultrahigh-speed readout systems is increasingly important. Here we present an ultra-fast readout
system developed to operate at 10Gbps, and intended to surpass a more conventional highlyparallel LVDS bus approach. The system generates a 5GHz clock (LC Oscillator), scrambles
and serialises the parallel input data in accordance with the Aurora 64b66b protocol, and
transmits the data off-chip through a Current Mode Logic (CML) line-driver at 10Gbps. A
prototype is under evaluation having been fabricated in early 2018 on a 65nm Multi-Project
Wafer. Serialiser ASIC ran at 10.312Gbps under test for 60 hours without a bit-error event.