With future pixel ASICs trending towards mega-frame rate readout, the development of ultrahigh-speed readout systems is increasingly important. Here we present an ultra-fast readout
system developed to operate at 10Gbps, and intended to surpass a more conventional highlyparallel LVDS bus approach. The system generates a 5GHz clock (LC Oscillator), scrambles
and serialises the parallel input data in accordance with the Aurora 64b66b protocol, and
transmits the data off-chip through a Current Mode Logic (CML) line-driver at 10Gbps. A
prototype is under evaluation having been fabricated in early 2018 on a 65nm Multi-Project
Wafer. Serialiser ASIC ran at 10.312Gbps under test for 60 hours without a bit-error event.
An Ultra-Fast 10Gb/s 64b66b Data Serialiser Backend in 65nm CMOS Technology
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Pre-published on:
July 04, 2019
Published on:
July 25, 2019
Abstract
DOI: https://doi.org/10.22323/1.343.0088
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Copyright owned by the author(s) under the term of the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
Copyright owned by the author(s) under the term of the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.