A System-Verilog Verification Environment for the CIC Data Concentrator ASIC of the CMS Outer Tracker Phase-2 Upgrades
June 24, 2019
July 25, 2019
The foreseen Phase-2 upgrades at the LHC present very challenging requirements for the front-end readout electronics of the CMS Outer Tracker detector. High data rates in combination with the employment of a novel technique for rejecting locally low transverse momentum particles as well as the strict low power consumption constraints require the implementation of an optimized readout architecture and specific interconnect synchronization schemes for its components.
This work focuses on the development and the verification of the Concentrator IC (CIC) ASIC, a 65 nm digital chip featuring high input and output data rates, in the context of the readout chains incorporating all front-end ASICs: namely the Macro Pixel ASIC (MPA), Short Strip ASIC (SSA) for the Pixel-Strip (PS) modules and the CMS Binary Chip (CBC) for Strip-Strip (2S) Modules. The CIC ASIC receives high data rate (320 MHz) digital streams from eight Front-end ASICs via a total of 48 differential lines and transmits them through seven differential lines operating at 320 MHz or 640 MHz, depending on the occupancy of the detector module.
A complex system level simulation environment based on the System-Verilog hardware description language and on the Universal Verification Methodology (UVM) platform has been adapted and extended to help the CIC development and verification simulating the complete readout chains from the particle event to the output of the modules.
The paper is composed of four sections: the first one describes the pT module concept, the second presents the UVM environment for MPA/SSA ASICs adapted and extended to include the CIC, the third one shows the readout-chain forecasted performances and show some examples of usage of this framework. The last section presents the PS module efficiency as a function of the stub occupancy for different CIC output frequencies.
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