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Volume 343 - Topical Workshop on Electronics for Particle Physics (TWEPP2018) - Posters
A high speed transmitter circuit for the ATLAS/CMS HL-LHC pixel readout chip
T. Wang,* T. Hemperek, H. Krüger, K. Moustakas, P. Rymaszewski, M. Vogt
*corresponding author
Full text: pdf
Pre-published on: 2019 May 21
Published on: 2019 July 25
In order to satisfy the high output bandwidth requirement imposed by the High Luminosity LHC, a high speed transmitter circuit was designed and integrated into the RD53A demonstrator chip for the phase 2 ATLAS/CMS pixel detector upgrade. A clock and data recovery circuit recovers clock from the 160 Mb/s data stream received by the chip, and provides the high speed clock to the serializer, where the 1.28 Gb/s output stream is formed from the 20-bit data words provided by the data encoding logic. The output stage employs a three-tap current-mode logic cable driver with adjustable tap weights for optimal pre-emphasis in order to compensate for the high frequency loss of the foreseen low mass cable. Each RD53A chip includes four output data lines, offering in total 5.12 Gb/s output bandwidth. The RD53A chip has been fabricated in a 65 nm CMOS technology. The output jitter was measured to be $\sim$ 20 ps (1 $\sigma$) with pseudo random data at the nominal speed of 1.28 Gb/s.
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