Characterization of the first prototype of the Silicon-Strip readout ASIC (SSA) for the CMS Outer-Tracker phase-2 upgrade
A. Caratelli*, S. Scarfi, D. Ceresa, K. Kloukinas, J. Kaplon, J. De Clercq, M. Haranko, Y. Leblebici on behalf of the CMS Tracker Group
May 21, 2019
July 25, 2019
The silicon strip readout ASIC (SSA) for the CMS Outer Tracker Pixel-Strip (PS) module was prototyped in a 65nm CMOS technology and characterized utilizing a custom made test bench based on the FC7 µTCA FPGA card. The ASIC has been evaluated and characterized under different working temperatures and radiation levels up to 200Mrad. Measurements show a frontend gain between 35 and 54mV/fC and an average noise of <330e-, meeting the specification of noise performance. The measured peaking time for an injected charge between 0.5fC and 8fC is 19ns allowing to detect consecutive particle events in combination with the zero dead-cycle binary readout. The embedded trimming circuit allows to obtain a measured threshold spread smaller than 55e- between channels. The measured power consumption is 60mW and thus within the strict power budget of the PS modules. The performance characterization results and radiation tolerance test results of the first SSA silicon prototype are presented.
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