Volume 364 - European Physical Society Conference on High Energy Physics (EPS-HEP2019) - Detector R&D and Data Handling
The ATLAS Trigger and Data Acquisition Upgrades for the High-Luminosity LHC (HL-LHC)
M. Valente* on behalf of the ATLAS collaboration
*corresponding author
Full text: pdf
Pre-published on: June 10, 2020
Published on:
Abstract
The ATLAS experiment at CERN has started the construction of upgrades for the High Luminosity LHC (HL-LHC), with collisions due to start in 2026. In order to deliver an order of magnitude more data than previous LHC runs, 7 TeV protons will collide at 14 TeV with an instantaneous luminosity of up to $7.5 \cdot 10^{34}\;\text{cm}^{-2}\text{s}^{-1}$, resulting in much higher pileup and data rates than the current experiment was designed to handle. While this is essential to realise the physics program, it presents a huge challenge for the detector, trigger, data acquisition and computing. The detector upgrades themselves present new requirements and opportunities for the trigger and data acquisition system. The approved baseline design of the TDAQ upgrade comprises: a hardware-based low-latency real-time trigger operating at 40 MHz, data acquisition which combines custom readout with commodity hardware and networking to deal with 5.2 TB/s input, and an event filter running at 1 MHz, which combines offline-like algorithms on a large set of commodity servers and hardware tracking. Commodity servers and networks are used, with custom ATCA boards, high speed links and powerful FPGAs deployed in the low-latency parts of the system. Offline-style clustering and jet-finding in FPGAs, and track reconstruction with Associative Memory ASICs and FPGAs are designed to combat pileup in the hardware trigger and the event filter respectively. This document reports recent progress on the design of the system and the performance on key physics processes.
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