CATIA: APD readout ASIC for the CMS phase 2 ECAL electronics upgrade
March 09, 2020
April 21, 2020
The incoming LHC upgrade to HL‒LHC calls for a change of the ECAL front-end electronics design in order to maintain the present performance of the detector while facing a higher instantaneous luminosity and to optimize the timing resolution while using the existing crystals and APDs. The design of the new front-end electronics is based on the cascading of two ASIC: a fast, dual gain trans-impedance amplifier designed in a 130 nm CMOS process (named CATIA) and a dual ADC designed in a 65 nm CMOS process. The latest test‒beam and laboratory test results of CATIA coupled with an ADC will be presented.
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