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Volume 370 - Topical Workshop on Electronics for Particle Physics (TWEPP2019) - Asic
The lpGBT PLL and CDR Architecture, Performance and SEE Robustness
S. Biereigel,* S. Kulis, R. Francisco, P.V. Leitao, P. Leroux, P. Moreira, J. Prinzie
*corresponding author
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Pre-published on: 2020 March 06
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We present the design, architecture and experimental results of the low jitter Clock and Data Recovery (CDR) and Phase Locked Loop (PLL) circuit in the Low-Power Gigabit Transceiver (lpGBT) ASIC. This circuit includes a low noise radiation-tolerant integrated LC-oscillator with a nominal frequency of 5.12 GHz to support a 10.24 Gbps uplink and a 2.56 Gbps downlink CDR. This CDR employs a novel loop architecture with a high-speed feed forward loop stabilization technique. A test circuit was fabricated in a 65 nm CMOS technology and has been tested experimentally for correct operation in the foreseen radiation environment.
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