The CERN-RD50 collaboration has ongoing research to further develop monolithic High Voltage-CMOS (HV-CMOS) sensors in a 150 nm process for future particle physics experiments. As a part of this research programme, a test chip (RD50-MPW2) that implements new methodologies for low leakage current and fast and low-noise readout circuitry has been designed and submitted for fabrication. This article presents the design details and simulation results of the 8 × 8 matrix of high-speed monolithic HV-CMOS pixels included in RD50-MPW2, in which two flavours of fast pixels are implemented: a conventional continuous-reset pixel and a switched-reset pixel with a novel asynchronous switched-reset scheme.