The Phase-II Upgrade of the ATLAS TileCal requires a new readout architecture with a fully digital trigger system in order to cope with the HL-LHC requirements. The on-detector readoutm electronics will transmit digitized data to 32 Tile PreProcessor modules in the counting rooms at the LHC frequency, transmitting selected data to the FELIX system and interfacing with the trigger systems. Each Tile PreProcessor module is composed of 4 Compact Processing Modules with single-width AMC form factor and one full-size ATCA carrier with 4 slots. This contribution presents the design of the first Compact Processing Module prototypes, and reviews the design of the Tile
PreProcessor Demonstrator board for the TileCal Demonstrator programme.