PoS - Proceedings of Science
Volume 370 - Topical Workshop on Electronics for Particle Physics (TWEPP2019) - Systems, Planning, Installation, Commissioning and Running Experience
First results from the CIC data aggregation ASIC for the Phase 2 CMS Outer Tracker
B. Nodari,* G. Bergamin, L. Caponetto, A. Caratelli, D. Ceresa, J. De Clercq, G. Galbit, S. Jain, K. Kloukinas, S. Scarfi, S. Seif El Nasr-Storey Sebastien Viret on behalf of the CMS Tracker Group
*corresponding author
Full text: pdf
Pre-published on: March 06, 2020
Published on: April 21, 2020
The Concentrator Integrated Circuit (CIC) ASIC is a front-end chip for both Pixel-Strip (PS) and Strip-Strip (2S) modules of the future Phase 2 CMS Outer Tracker at the High-Luminosity LHC (HL-LHC). Prototyped in a 65 nm CMOS technology, the CIC aggregates the digital data coming from eight upstream front-end chips, formatting it into data packets containing the trigger information from eight bunch crossings and the raw data from events passing the Level 1 (L1) trigger, before transmission to the lpGBT. The role of the CIC in the readout chain is to provide an extra factor of data reduction by grouping data over time and space. A first prototype, the CIC1, integrating all functionalities for system level operation, has been tested in early 2019. A brief description of the functionalities and the test results obtained concerning the performance characterization and the radiation tolerance of the chip are presented in this contribution.
DOI: https://doi.org/10.22323/1.370.0102
How to cite

Metadata are provided both in "article" format (very similar to INSPIRE) as this helps creating very compact bibliographies which can be beneficial to authors and readers, and in "proceeding" format which is more detailed and complete.

Open Access
Creative Commons LicenseCopyright owned by the author(s) under the term of the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.