The first running implementation on FPGA of a histogram-based trigger primitive generator for the CMS Drift Tubes at the High Luminosity LHC is presented. The foreseen architecture requires that raw charge collection times, measured for each tube by means of a TDC, are processed in the back-end to generate trigger primitives, identifying the parent bunch crossing and measuring the track parameters. We review the design of a parent bunch crossing evaluation, its implementation on FPGAs of the Xilinx UltraScale family by means of High-Level Synthesis, and the performance of a demonstrator board of such a trigger.