The ATLAS Hardware Track Trigger performance studies for the HL-LHC
October 16, 2020
January 11, 2021
For the High-Luminosity LHC, planned to start in 2027, the ATLAS experiment will be equipped with the Hardware Tracking for the Trigger (HTT) system, a dedicated hardware system able to reconstruct tracks in the silicon detectors with short latency. The evolved trigger and data acquisition system design consists of a two-level hardware trigger in which the HTT is used in a low-latency mode (L1Track), providing tracks in regions of ATLAS at a rate of up to 4 MHz, with a latency of a few tens of micro-seconds. Different readout scenarios for the silicon pixel layers of the inner detector are under study. While the full simulation of HTT is under development, an emulation procedure is developed to study the impact of L1Track-like tracking resolutions on physics benchmark channels. In this document we describe the status of the ongoing HTT performance studies for the HL-LHC trigger menu, covering the impact on $b$-tagging and on multi-jet and leptonic trigger selections.
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