The ATLAS inner detector will be replaced by an all-silicon detector for the HL-LHC upgrade
around 2025. The innermost five layers of the detector system will be pixel detector layers which
will be most challenging in terms of radiation hardness, data rate and readout speed. Aserial power
scheme will be used for the pixel layers to reduce the material budget and power consumption in
cables. New elements are required to operate and monitor a serially powered detector including a
detector control system, constant current sources and front-end electronics with shunt regulators.
Prototypes for all sections of the ITk pixel detector are built to verify the concept and operate
multiple serial power chains as a system test. The evaluation of both the readout of multi-modules
and mechanical integration are further aims of the prototyping campaign. In the contribution,
results will be presented of this prototyping effort. Moreover, details and features of serial
powering for full detector systems will be given.