The electronics of the Compact Muon Solenoid (CMS) Drift Tube (DT) chambers will need to be replaced for the High Luminosity LHC (HL-LHC) operation, also called Phase 2, due to the increase of occupancy and trigger rates in the detector, which cannot be sustained by the present system. New electronics are being designed that will forward asynchronously the totality of the chamber signals to the counting room, at full resolution. The new back-end system will be in charge of building the trigger primitives (TP) of each chamber out of this asynchronous information, aiming at achieving resolutions comparable to the ones of the offline reconstruction. The new improved functionality will help to improve the resilience to potential ageing situations. An algorithm for the TP generation that will run in this new back-end system has been developed and implemented in firmware. The performance of this algorithm has been validated through different methods: from a software emulation approach to hardware implementation tests. The performance obtained is very good, with optimal timing and position resolutions, close to the ultimate performance of the DT chambers. One important validation step was including the implementation of this algorithm in a prototype chain of the HL-LHC electronics, which has been operated with real DT chambers during cosmic data taking. The new TP generation has been implemented in the so-called AB7, spare uTCA boards from the present DT system which host Xilinx Virtex 7 FPGAs. The performance of this prototyping system has been verified and will be presented in this contribution, showing the feasibility of the design for the expected functionality
during HL-LHC.