The Thin Gap Chamber system of the LHC-ATLAS is responsible for triggering muons in the endcap region at the hardware trigger stage. The frontend system of Thin Gap Chamber will be upgraded for HL-LHC to send binary hit-map at every Bunch Crossing to the backend system, where track reconstruction and $p_{\rm T}$ determination is performed to generate inputs to the Level-0 trigger. The new system incorporates improvements in Bunch Crossing Identification performance by fine-tuned clock distribution and capability of fine timing calibration. The Primary processor board is in charge of Bunch Crossing Identification and data transmission to the backend. An independent control module, named JTAG Assistance Hub, will take responsibility for FPGA configuration and clock phase monitoring of the Primary processor board with an SoC-based design. JTAG Assistance Hub also takes role in triggering the reconfiguration of frontend electronics for unrecoverable Single Event Upset errors by radiation effects. The timing calibration methodology for fine-tuning the clock phase and signal timing is realized with highly-extended flexibility in the Phase-2 system, exploiting the experience accumulated through the construction, commissioning, and operation of the existing Thin Gap Chamber system. System-level commissioning has been launched at KEK with prototypes of Primary processor boards and JTAG Assistance Hub and Amplifier-Shaper-Discriminator cards. The full-chain testbed system allows us to demonstrate fundamental functionalities of Trigger, Readout, Control and Calibration: clock phase fine-tuning, signal timing calibration, and hit readout with test pulse injection to Amplifier-Shaper-Discriminator cards with adjusted timing parameters.