PoS - Proceedings of Science
Volume 414 - 41st International Conference on High Energy physics (ICHEP2022) - Poster Session
Performance and Improvements of the ATLAS Level-1 Muon Trigger for Run 3
Y. Hayashi*  on behalf of the ATLAS Collaboration
Full text: pdf
Pre-published on: October 24, 2022
Published on: June 15, 2023
The LHC is starting the Run 3 operation aiming the luminosity leveled at a peak of \(2.0\times10^{34} \ \rm{cm}^{-2} \rm{s}^{-1}\) for 6-10 hours. In order to cope with the high event rate, the ATLAS Level-1 Muon trigger system has been upgraded. The Level-1 Muon trigger system identifies muons with high transverse momentum by combining data from fast muon trigger detectors, the Resistive-Plate Chamber (RPC) and the Thin-Gap Chamber (TGC). Since Run 3, the system introduced the improvement of the trigger logic using the new detectors "New-Small-Wheel (NSW)" and "RPC-BIS78", which are located in the inner station region for the endcap muon trigger. Information provided by the NSW and RPC-BIS78 can be used as part of the muon trigger logic to enhance the performance. In order to receive the extended data, new electronics have been developed, including the trigger processor board known as Sector Logic (SL). The SL board consists of a modern FPGA to make use of Multi-Gigabit transceiver technology, which will be used to receive data from the new detectors. The readout system for trigger data has also been designed for the extended trigger readout, with the data transfer implemented with TCP/IP instead of a dedicated ASIC, replacing the use of custom readout electronics with commodity servers and network switches to collect, format, and send the data. The trigger data readout is used for trigger logic commissioning, validation, performance measurement, and further improvements. These proceedings describe the upgrades of the Level-1 Muon trigger system. Particular emphasis is placed on the first results from the early phase of commissioning in 2022. The latest status of the system, the improvement, and expected performance are presented.
DOI: https://doi.org/10.22323/1.414.1004
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