PoS - Proceedings of Science
Volume 414 - 41st International Conference on High Energy physics (ICHEP2022) - Operation, Performance and Upgrade (incl. HL-LHC) of Present Detectors
Development of the ATLAS Liquid Argon Calorimeter Readout Electronics for the HL-LHC
A. Deiana
Full text: pdf
Pre-published on: November 27, 2022
Published on:
Abstract
A new era of hadron collisions will start around 2029 with the High-Luminosity LHC, that will allow to collect ten times more data than what has been collected so far. This is possible thanks to the expected higher instantaneous luminosity and higher number of collisions per bunch crossing. To meet the new trigger and data acquisition requirements and to withstand the high expected radiation doses at the High-Luminosity LHC, the ATLAS Liquid Argon Calorimeter readout electronics will be upgraded. The triangular calorimeter signals will be amplified and shaped by analogue electronics over a dynamic range of 16 bits, with low noise and excellent linearity. Developments of low-power preamplifiers and shapers to meet these requirements are ongoing in 130 nm CMOS technology. In order to digitize the analogue signals on two gains after shaping, a radiation-hard, low-power 40 MHz 14-bit ADCs is being developed using a pipeline+SAR architecture in 65 nm CMOS. The characterization of the prototypes of these on-detector components is promising and likely will fulfill all the requirements. The signals will be sent at 40 MHz to the off-detector electronics, where FPGAs connected through high-speed links will perform energy and time reconstruction through the application of corrections and digital filtering. Reduced data will be then sent with low latency to the level-0 trigger-system, while the full data will be buffered until the reception of the trigger decision signal. For a triggered event, the full data will be sent to the ATLAS readout system. The data-processing, control, and timing functions will be realized with dedicated boards using the ATCA technology. Here, the results of tests of prototypes of the on-detector components will be presented. The design of the off-detector boards along with the performance of the first prototypes will be discussed. In addition, the architecture of the firmware and processing algorithms will be shown.
DOI: https://doi.org/10.22323/1.414.0668
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