During the Long Shutdown 2 of the LHC, the ATLAS detector underwent its Phase-1 Upgrade in order to better handle the increased luminosity in LHC Run 3 and beyond. A significant part of this upgrade comprises new custom hardware for the first-level calorimeter-trigger path using state-of-the-art FPGAs. An overview of the different subsystems, their capabilities and roles in the overall ATLAS trigger and data acquisition architecture, and their relevance for the ATLAS physics program is presented. Finally, exemplary preliminary performance estimates are discussed.