Silicon-On-Insulator (SOI) technology has been regarded as a best match technology for monolithic radiation pixel detector from a very early stage. However, major issues can severely affect the operability of the detector, such as the back-gate effect, the coupling between sensors and readout electronics and Total Ionization effect (TID).
We proved to have solved these issues by developing new technologies such as buried well and double SOI wafer/process. Transistor performance degradation by radiation was studied in detail, and we can successfully increase radiation hardness more than 100 kGy(Si) by changing the dose level of the Lightly Doped Drain (LDD) region.
In addition, the layout size of the pixel circuit is shrunken by introducing PMOS and NMOS active merge technique. This enables much smaller layout size than conventional CMOS process while keeping high enough analog operation voltage.
The process technologies we developed and a few examples of SOI detectors are described.