A 2.56 GHz Radiation Hard Phase Locked Loop ASIC for High Speed Serial Communication Links
J. Prinzie*, M. Steyaert, P. Moreira and P. Leroux
Pre-published on:
March 05, 2018
Published on:
March 20, 2018
Abstract
This works presents the design and experimental study of a radiation hardened Phase Locked Loop (PLL) for high speed serial-communication links. These research results are used for the LpGBT (Low Power Gigabit Transceiver) chip which will be widely used for optical data-links between the detectors and the counting rooms in the HL LHC experiments. The PLL features a novel LC-oscillator architecture which is not sensitive to single-event transients. Additionally, the circuit uses triple-modular redundancy and is designed in a 65 nm CMOS technology.
DOI: https://doi.org/10.22323/1.313.0002
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