A 2 Gsps Waveform Digitizer ASIC in CMOS 180 nm Technology
J. Qin*, L. Zhao, Y. Guo, B. Cheng, Y. Lu, H. Chen, S. Liu and Q. An
Pre-published on:
March 05, 2018
Published on:
March 20, 2018
Abstract
The design and measurement results of a waveform digitizer based on the Switched Capacitor Array (SCA) architecture, fabricated in CMOS 180 nm technology, are presented. The prototype ASIC containing two channels inside is fully functional at a sampling rate of 2 Gsps with an analogue -3 dB bandwidth of about 450 MHz. Each channel integrates 128 sampling cells and a ramp-compare ADC. With this ASIC, sine waveform and reconstructed PMT waveform recording tests were conducted. We also evaluated its performance on fast pulse timing, and the timing precision is proved to be better than 20 ps RMS after a series of correction strategies.
DOI: https://doi.org/10.22323/1.313.0007
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