To cope with the enhanced luminosity delivered by the Large Hadron Collider from 2021 onwards, the ATLAS experiment has planned several upgrades. The first level trigger based on calorimeter data will be upgraded to exploit fine-granularity readout using a new system of Feature EXtractors (FEXs, FPGA based trigger boards), each optimized to trigger on different physics objects.
This contribution is focused on the jet FEX. The main challenges of such a board are the input bandwidth of up to 3.1 Tbps, dense routing of high-speed signals and power consumption. The design, PCB simulations and results of integrated tests of a prototype are shown in this document.