Improved Tapped-Delay-Line Time-to-Digital Converter with Time-over-Threshold measurement for a new generation of Resistive Plate Chamber detectors
2019 May 21
2019 July 25
To exploit the timing performance of a new generation of Resistive Plate Chamber (RPC) detectors, we propose a TDC using a signal-reshaping approach to minimize bubble length (bits of uncertain data) and thus to improve the time measurement resolution. It includes two encoders to detect independently the signal’s leading/trailing edges in a 64-bit window, instead of taking the whole delay line’s length over hundreds of bits. This saves implementation resources. Our proposed TDC has been implemented on a FPGA (Cyclone V GT device, 5CGT–D9-C7N) in 65 channels in parallel. Test results give evaluated precision of measurements in RMS values: 10.0ps for leading edge, 14.1ps for trailing edge and 18.1ps for ToT respectively. The TDC can operate at a minimum pulse width of 2ns for its input pulsed signal.