PoS - Proceedings of Science
Volume 364 - European Physical Society Conference on High Energy Physics (EPS-HEP2019) - Detector R&D and Data Handling
New Level-1 jet feature extraction modules for ATLAS phase-I upgrade
R.J. Wang*, B. Bauss, A. Brogna, V. Büscher, R. Degele, H. Herr, C. Kahra, S. Rave, E. Rocco, U. Schäfer, J. Schaffer, J. Souza, M. Weirich and D.B. Ta
Full text: pdf
Pre-published on: October 04, 2020
Published on: November 12, 2020
After the Long Shutdown 2 (Dec.~2018 -- Feb.~2021), the LHC will be a new machine in many respects and produce collisions with a center-of-mass energy at or near 14 TeV. The instantaneous luminosities can be expected to reach $2\times10^{34}$ cm$^{-2}$s$^{-1}$, which is two times the original design value. The mean number of interactions per bunch crossing is expected to go up to 80. To meet the challenges of the high-luminosity environment (much higher event rates and pileup level), several major upgrades will be installed during the Long Shutdown 2 in the ATLAS detector. As a part of the updates, the Level-1 calorimeter trigger will be upgraded to exploit higher granularity data compared to those available during Run 2 by using a new system of feature extraction modules, which each reconstructs different physics objects at Level-1.

The Jet Feature Extractor (jFEX) is one of three feature extraction modules and has been conceived to identify small-/large-area jets, large-area $\tau$ leptons, missing transverse energy and the total sum of the transverse energy. The Xilinx Virtex UltraScale+ FPGA fulfills the physics requirements of significant processing power and large input bandwidth within a tight latency budget. The modular design optimizes a large number of high-speed signals within the limited space of an ATCA board. To guarantee the signal integrity, the board design has been accompanied by simulation of the power, current, and thermal distributions. The printed circuit board has a 24-layer stack-up and uses the MEGTRON6 material, which is commonly used for signal transmission above 10 Gb/s.

This contribution focuses on the technological aspects of the jFEX module, reporting on the simulation studies and the design solutions of the board. Two jFEX prototypes and one pre-production module have been produced and tested at CERN with other systems, and these test results are presented. The firmware implemented on the trigger board will be illustrated in connection with the FPGA performance and board power consumption. The whole jFEX system, consisting of 6 boards, will be produced by the end of 2019 to allow the installation and commissioning of the full system in time for the LHC restart at the beginning of 2021.
DOI: https://doi.org/10.22323/1.364.0201
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