A 32-channel, 15 ps resolution, Kintex 7 FPGA-based data acquisition (DAQ) system for time-of-flight (TOF) and time-over-threshold (TOT) SiPM readout is demonstrated along with a comparison to previous works. Focusing on modern FPGA concerns such as clock skew and bin realignment, the implementation difficulties of FPGA-based TDCs are discussed including bubble error, zero length bins, inter-clock region nonlinearity, and chain overflow. Linearity of the TDC is improved by multichain averaging with comparison of 1, 2, and 4 chains pre and post-calibration. Measurement results of the proposed TDC include 11 ps mean bin size, a differential nonlinearity (DNL) of less than 4 ps, and an integral nonlinearity (INL) of less than 10 ps.