Recent depleted CMOS developments within the CERN-RD50 framework
March 13, 2020
September 14, 2020
Depleted CMOS sensors are groundbreaking position sensitive detectors that offer a competitive and cost-effective solution for a large range of particle tracking applications. In spite of their substantial advantages, these sensors require further research to become even more performant and meet the ever more demanding requirements of particle physics experiments planned for the near future. In this context, the CERN-RD50 collaboration has started a new R&D programme to study and develop depleted CMOS sensors as one of its main priorities.
This article presents the depleted CMOS R&D programme within the CERN-RD50 collaboration. It describes the design aspects of the two prototype ASICs developed so far, which are in a 150 nm High Voltage-CMOS (HV-CMOS) process and manufactured on high resistivity substrates. The first prototype ASIC, named RD50-MPW1 and delivered after fabrication in April 2018, integrates a matrix of 50 μm x 50 μm pixels with all the analogue and digital readout electronics for column drain readout embedded in their sensing areas. The second prototype ASIC, named RD50-MPW2 and delivered after fabrication in January 2020, integrates a matrix of 60 μm x 60 μm pixels with analogue readout electronics to reduce the sensor response time. RD50-MPW2 incorporates new methods to optimise the leakage current of the sensor. The article discusses laboratory measurements of the performance evaluation of RD50-MPW1, while those of RD50-MPW2 will be published elsewhere.
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