For the HL-LHC upgrade the current ATLAS Inner Detector is replaced by an all-silicon system. The Pixel Detector will consist of 5 barrel layers and a number of rings, resulting in about 14$~\mathrm{m^2}$ of instrumented area. Due to the huge non-ionizing fluence (over 2e16$~\mathrm{n_{eq}/cm^2}$ and ionizing dose (larger than 5 MGy), the two innermost layers, instrumented with 3D pixel sensors (L0) and 100$~\mathrm{\mu m}$ thin planar sensors (L1) will be replaced after about 5 years of operation. All hybrid detector modules will be read out by novel ASICs, implemented in 65 nm CMOS technology, with a bandwidth of up to 5 Gb/s. Data will be transmitted optically to the off-detector readout system. To save material in the servicing cables, serial powering is employed for low voltage. Large scale prototyping programmes are being carried out by all sub-systems. This paper will give an overview of the layout and current status of the development of the ITk Pixel Detector.