The Monolithic Stitched Sensor (MOSS) chip is the first stitched prototype developed for the upgrade of the Inner Tracking System 3 (ITS3) vertexing detector in the ALICE experiment at the LHC. This upgrade aims at reducing the material budget to 0.05$\%$ X$_{0}$ per layer, achievable with a large bendable single-die sensor by replacing the water-cooling system with air flow and minimizing other external circuit components. Thus the only material remaining in the acceptance is the silicon itself. Benefiting from the stitching technology, the MOSS chip measures 1.4 cm $\times$ 26 cm and is designed to explore the feasibility and yield factors of wafer-scale sensors. The chip is implemented in a 65 nm CMOS imaging technology, studied in the framework of the CERN-EP R&D. Composed of one left endcap, 10 repeated sensor units, and one right endcap, it features more than 20 sub-units to increase power granularity and hence resilience to manufacturing faults. Such design presents a number of challenges. This contribution gives an overview and then focuses on the multiple-domain power plan and its impact on domain isolation and electrostatic discharge protection.