The increase in luminosity and pileup foreseen for future colliders has recently pushed central pixel detector technology towards an increase in timing resolution. Increased time resolution can ease track reconstruction by adding a more precise timestamp to events for better track separation. An alternative approach to timing with silicon pixel detectors is proposed in this paper. Current approaches are based either on amplitude increase due to avalanche charge multiplication or in the reduction of charge collection time in a 3D geometry detector. Both approaches uses charge integration amplifiers for signal pre-amplification. The main feature of the proposed approach is based on current preamplifier signal readout and a more comprehensive approach to time resolution improvement. An additional aspect of this approach is that it shifts the attention from the detector design to the readout electronics design. The current pulse of a silicon detector has an intrinsically fast (in the order of 5 ps) rise-time however the actual rise-time of a detector connected to a current (low impedance) preamplifier is limited by the RC product of the input resistance and the capacitance of the detector/preamplifier interface and the bandwidth of the preamplifier itself; using low impedance amplifier and low capacitance pixel detector the rise-time of this pulse can be kept below 200 ps. The amplitude of the signal can be increased by bias overvoltage and temperature reduction (increases mobility shrinking the current pulse duration). Furthermore low temperature operation (- 30 °C or less) and the low input capacitance of the detector can help to reduce noise. The combination of reduced rise-time, increased amplitude and reduced noise can tentatively improve the overall time resolution below 20 ps which is considered the best result achieved.