High Voltage/High resistivity Depleted Monolithic Active Pixel Sensors (HV/HR-DMAPS) is a technology which is becoming of great interest for high energy physics applications.
With respect to hybrid pixel detectors the monolithic approach offers the main advantages of reduced material budget and production costs due to the absence of the bump bonding process. This aspect is important especially when large areas need to be covered as in the tracking detectors of the LHC experiments. Thus, the possibility of employing this technology in the outermost layers of the upgraded ATLAS pixel detector at the HL-LHC is being investigated.
Different HR/HV-DMAPS prototypes have been recently developed for the future ATLAS Inner Tracker (ITk) with the aim of studying their radiation hardness and the feasibility of producing large area devices.

The H35DEMO is a large area demonstrator chip for the ITk designed by KIT, IFAE and University of Liverpool and produced in AMS 350 nm HV-CMOS technology with an engineering run on four different substrate resistivities: 20, 80, 200 and 1000 $\mathrm{\Omega cm}$. It consists of four large matrices, two of which include digital electronics and are thus fully monolithic.
One, called CMOS matrix, has comparators made of CMOS transistors in the periphery only, while the other, called NMOS matrix, includes also comparators made of NMOS transistors directly in the pixels. The other two matrices have only analog front-end electronics and are meant to be coupled to ATLAS FE-I4 chips.
All matrices feature pixels with a size of $\mathrm{(50\times250)\;\mu m^2}$ in which the analog electronics are embedded in a Deep N-WELL (DNWELL) also acting as collecting electrode.
A Data Acquisition (DAQ) system was developed at IFAE to read out and test the monolithic matrices of the H35DEMO both in the laboratory and with beam test experiments.
H35DEMO chips with a resistivity of 200 $\mathrm{\Omega cm}$ have been irradiated with reactor neutrons to a particle fluence of $1\times10^{15}$ $\mathrm{1\;MeV\;n_{eq}/cm^2}$, the expected fluence for the outermost pixel layer of ITk. The monolithic CMOS matrix of the H35DEMO chip was extensively characterised before and after irradiation in beam tests at Fermilab and DESY, with proton and electron beams, respectively.
Results after irradiation show good performance in terms of hit efficiency with thresholds of about 1800 e and a bias voltage of 150 V.

Another production of monolithic HV-CMOS prototypes in LFoundry 150 nm technology (LF2) has been recently completed. It includes sensors with a similar DNWELL concept as the H35DEMO but with a smaller pixel size of $\mathrm{(50\times50)\;\mu m^2}$. Preliminary measurements of leakage current of the LF2 chips have been preformed showing good agreement with what expected from the foundry process.