PoS - Proceedings of Science
Volume 343 - Topical Workshop on Electronics for Particle Physics (TWEPP2018) - Asic
RD53A: a large scale prototype for HL-LHC silicon pixel detector phase 2 upgrades
E. Monteil,* M. Barbero, D. Fougeron, S. Godiot, M. Menouni, P. Pangaud, A. Rozanov, P. Breugnon, M. Bomben, G. Calderini, F. Crescioli, G. Marchiori, D. Dzahini, F.E. Rarbi, R. Gaglione, H. Krueger, T. Hemperek, F. Huegging, P. Rymazewski, M. Vogt, T. Wang, N. Wermes, M. Karagounis, C. Marzocca, F. Loddo, F. Licciulli, A. Andreazza, V. Liberali, A. Stabile, L. Frontini, M. Bagatin, D. Bisello, S. Gerardin, S. Mattiazzo, A. Paccagnella, D. Vogrig, S. Bonaldo, N. Bacchetta, L. Gaioni, M. Manghisoni, V. Re, E. Riceputi, G. Traversi, L. Ratti, C. Vacchi, K. Androsov, R. Beccherle, G. Magazzù, M. Minuti, F. Morsani, F. Palla, S. Poulios, G.M. Bilei, M. Menichelli, P. Placidi, S. Marconi, G. Dellacasa, N. Demaria, G. Mazza, E. Monteil, L. Pacher, A. Rivetti, A. Paternò, D. Gajanna, V. Gromov, R. Kluit, A. Vitkovskiy, T. Benka, M. Havranek, Z. Janoska, M. Marcisovsky, G. Neue, L. Tomasek, V. Kafka, V. Vrba, E. Lopez-Morillo, F.R. Palomo, F. Munoz, I. Vila, E. Jiménez, D. Abbaneo, J. Christiansen, S. Orfanelli, S.J.M. Bell, M. Prydderch, S. Thomas, D.C. Christian, G. Deptuch, F. Fahim, J. Hoff, T. Zimmerman, S. Miryala, M. Garcia-Sciveres, D. Gnani, A. Krieger, K. Papadopoulou, T. Heim, R. Carney, B.P. Nachman, C. Renteira, V. Wallangen, M.R. Hoeferkamp, S. Seidel, M. Daas, Y. Dieter, K. Moustakas, A. Stiller, R. Lipton, T.C. Liu
*corresponding author
Full text: pdf
Pre-published on: May 22, 2019
Published on: July 25, 2019
Abstract
The Phase 2 upgrades of silicon pixel detectors at HL-LHC experiments feature extreme require- ments, such as: 50x50 μm pixels, high rate (3 GHz/cm2), unprecedented radiation levels (1 Grad), high readout speed and serial powering. As a consequence a new readout chip is required. In this framework the RD53 collaboration submitted RD53A, a large scale chip demonstrator de- signed in 65 nm CMOS technology, integrating a matrix of 400×192 pixels. It features design variations in the analog and digital pixel matrix for testing purposes. An overview of the building blocks will be given together with test results on single chips.
DOI: https://doi.org/10.22323/1.343.0157
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