Design of a 4 ps radiation hardened TDC with an improved interpolation technique
B. Van Bockel*, J. Prinzie and P. Leroux
Pre-published on:
March 06, 2020
Published on:
April 21, 2020
Abstract
This paper presents a radiation tolerant single-shot time-to-digital converter (TDC) with a resolution of 4 ps, fabricated in a 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. To achieve the low resolution, the delay elements are implemented using a new interlocked interpolation technique to reduce the Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) error. The delay line is placed inside a Delay Locked Look (DLL) to compensate for Process, Voltage and Temperature (PVT) variations- and variations due to ionizing radiation.
DOI: https://doi.org/10.22323/1.370.0127
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