Design of a 4 ps radiation hardened TDC with an improved interpolation technique
March 06, 2020
April 21, 2020
This paper presents a radiation tolerant single-shot time-to-digital converter (TDC) with a resolution of 4 ps, fabricated in a 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. To achieve the low resolution, the delay elements are implemented using a new interlocked interpolation technique to reduce the Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) error. The delay line is placed inside a Delay Locked Look (DLL) to compensate for Process, Voltage and Temperature (PVT) variations- and variations due to ionizing radiation.
How to cite
Metadata are provided both in "article" format (very similar to INSPIRE) as this helps creating
very compact bibliographies which can be beneficial to authors and
readers, and in "proceeding" format
which is more detailed and complete.