The power attack of the hardware circuit is going through the steps of algorithm writen in FPGA, power consumption, data processing and analysis. In order to solve the problem of the
existing power attack experimental platform because the processing steps are too scattered, feature complex operations and other issues, we've thus developed a higher degree of integration
of the experimental platform. The advanced encryption standard (AES) algorithm is taken as an example to illustrate the whole process of implementing the correlation power analysis (CPA)
attack on the experimental platform. The AES algorithm will be downloaded to the SAKURA-G experiment board, acquire the algorithm runtime power leakage, carry out the energy analysis because related attacks on information may leak location, and restore the AES first round of the first byte of the key. Empirical results show that the comprehensive experimental platform will integrate
these steps into a platform, simplify the operation process,
ensure the accuracy of power acquisition, realize the parallel data processing and improve the accuracy and efficiency of power attack.