PoS - Proceedings of Science
Volume 313 - Topical Workshop on Electronics for Particle Physics (TWEPP-17) - ASIC
LAPA, a 5 Gb/s modular pseudo-LVDS driver in 180 nm CMOS with capacitively coupled pre-emphasis
R. Cardella*, I. Berdalović, N. Egidos Plaja, T. Kugathasan, C.A. Marin Tobon, H. Pernegger, P. Riedler and W. Snoeys
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Pre-published on: March 05, 2018
Published on: March 20, 2018
Abstract
A pseudo-LVDS driver has been designed in a 180 nm technology for operation up to 5 Gb/s.
It contains parallel main driver units based on an H-bridge circuit steering a current on an external load. The number of active units is adjustable, to reduce switching capacitance and static current, and hence power consumption, if a smaller current swing can be tolerated.
Pre-emphasis is applied with a capacitively coupled charge-injection circuit. In the nominal condition with a steering current of 4 mA over a 100 $\Omega$ termination resistor, it consumes 30 mW from a 1.8 V supply.
DOI: https://doi.org/10.22323/1.313.0038
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