PoS - Proceedings of Science
Volume 370 - Topical Workshop on Electronics for Particle Physics (TWEPP2019) - Radiation Tolerant Components and Systems
Study of SEU effects in circuits developed in 110 nm CMOS technology
D. Calvo,* P. De Remigis, M. Fisichella, R. Wheadon, A. Zambanini, S. Mattiazzo, E. Verroi, F. Tommasino
*corresponding author
Full text: pdf
Pre-published on: March 06, 2020
Published on: April 21, 2020
Channel configuration registers of a full size prototype for the custom readout circuit of silicon double-sided microstrips of PANDA Micro Vertex Detector were tested for upset effects. The ASIC is developed in a commercial 110 nm CMOS technology and implements both Triple Modular Redundancy and Hamming Encoding techniques. Results from tests with ion and proton beams show the robustness level of these two techniques against the upset effects and allow the evaluation of that commercial 110 nm technology in the PANDA experiment.
DOI: https://doi.org/10.22323/1.370.0126
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