A Real-Time Demonstrator for Track Reconstruction in the CMS L1 Track-Trigger System Based on Custom Associative Memories and High-Performance FPGAs
G. Magazzu'*,
C. Gentsos,
G. Fedi,
D. Magalotti,
A. Modak,
F. Palla,
G.M. Bilei,
S.R. Chowdhury,
B. Checcucci,
D. Tcherniakhovski,
G.C. Galbit,
G. Baulieu,
M.N. Balzer,
O. Sander,
S. Viret and
L. Storchi*: corresponding author
Pre-published on:
March 05, 2018
Published on:
March 20, 2018
Abstract
A Real-Time demonstrator based on the ATCA Pulsar-IIB custom board and on the Pattern Recognition Mezzanine (PRM) board has been developed as a flexible platform to test and characterize low-latency algorithms for track reconstruction and L1 Trigger generation in future High Energy Physics experiments. The demonstrator has been extensively used to test and characterize the Track-Trigger algorithms and architecture based on the use of the Associative Memory ASICs and of the PRM cards. The flexibility of the demonstrator makes it suitable to explore other solutions fully based on high-performance FPGA device.
DOI: https://doi.org/10.22323/1.313.0138
How to cite
Metadata are provided both in
article format (very
similar to INSPIRE)
as this helps creating very compact bibliographies which
can be beneficial to authors and readers, and in
proceeding format which
is more detailed and complete.