Volume 370 - Topical Workshop on Electronics for Particle Physics (TWEPP2019) - Programmable Logic, Design Tools and Methods
Multi-channel time-tagging module for fast-timing Resistive Plate Chamber detectors
X. Chen*, C. Combaret, C. Girerd, C. Guerin, I. Laktineh, X. Lin-Ma, L. Mirabito and G.n. Lu
*: corresponding author
Full text: pdf
Pre-published on: March 06, 2020
Published on: April 21, 2020
Abstract
A multi-channel time-tagging module is proposed for fast timing resistive plate chamber (RPC) detectors. It has been designed and implemented in a low-end and low-power cyclone V FPGA. Each channel mainly consists of a time-to-digital converter (TDC) in tapped-delay-line (TDL) architecture. The TDC has three main building blocks: tapped delay line (with registers and a AND logic), fine timestamp converter, and coarse timestamp generator. Several data processing techniques, including prior signal reshaping and noise-immune processing, have been adopted to minimize noise effects. The module has successfully been tested in all-channel simultaneous operation conditions, with 11 ps to 20 ps time resolution and full event-detecting efficiency for all the channels.
DOI: https://doi.org/10.22323/1.370.0093
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